Proceedings of ISP RAS

Test Program Generation for Microprocessors Based on Pipeline Hazards Templates.

D.N. Vorobyev, A.S. Kamkin.


In this work, a method for the automated test programs generation aimed at the verification of microprocessor control logic is considered. The method is based on formal specification of a microprocessor instruction set and description of pipeline hazards templates. The use of formal specifications allows automating development of test program generators and systematically testing control logic. At the same time, since the approach utilizes high-level descriptions that do not take into account cycle-accurate functioning of a pipeline, all the specifications and templates developed, as well as the constructed test programs, can be reused when the microarchitecture is modified. It makes it possible to apply the method at early stages of the microprocessor design cycle when frequent design changes are possible.


microprocessor verification, pipeline hazards, instruction set specification, test program generation.


Proceedings of the Institute for System Programming, vol. 18, 2010, pp. 91-114.

ISSN 2220-6426 (Online), ISSN 2079-8156 (Print).

Full text of the paper in pdf (in Russian) Back to the contents of the volume