Proceedings of ISP RAS


Mechanisms for functional testing of hardware models at different levels of abstraction.

A.S. Kamkin, M.M. Chupilko.

Abstract

It is known that at different design stages different representations of a target system are used (a general description of the system's architecture is step by step concretized up to a physical layout). Depending on the project maturity engineers apply different verification methods and, in particular, methods for developing reference models, which are used to check the design correctness (at the beginning of the design process only abstract models are applied; when the process is close to the end, models accuracy is increased).

Distinction in abstraction makes it difficult to reuse testbenches having been created at the early stages for verifying the same components some time later. In this paper, we suggest an approach to construct reference models and test oracles that eases testbench reuse thereby reducing verification costs.

Keywords

hardware design, functional verification, simulation-based verification, transaction level modeling

Edition

Proceedings of the Institute for System Programming, vol. 20, 2011, pp. 143-160.

ISSN 2220-6426 (Online), ISSN 2079-8156 (Print).

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