Proceedings of ISP RAS


MicroTESK-Based Test Program Generator for the ARMv8 Architecture

A.S. Kamkin (ISP RAS, Moscow, Russia, MSU, Moscow, Russia, MIPT, Dolgoprudny, Russia)
A.M. Kotsynyak (ISP RAS, Moscow, Russia)
A.S. Protsenko (ISP RAS, Moscow, Russia)
A.D. Tatarnikov (ISP RAS, Moscow, Russia)
M.M. Chupilko (ISP RAS, Moscow, Russia)

Abstract

ARM is a family of microprocessor instruction set architectures developed in a company with the same name. The newest architecture of this family, ARMv8, contains a large number of instructions of various types and is notable for its complex organization of virtual memory, which includes hardware support for multilevel address translation and virtualization. All of this makes functional verification of microprocessors with this architecture an extremely difficult technical task. An integral part of microprocessor verification is generation of test programs, i.e. programs in the assembly language, which cause various situations (exceptions, pipeline stalls, branch mispredictions, data evictions in caches, etc.). The article describes the requirements for industrial test program generators and presents a generator for microprocessors with the ARMv8 architecture, which has been developed with the help of MicroTESK (Microprocessor TEsting and Specification Kit). The generator supports an instruction subset typical for mobile applications (about 400 instructions) and consists of two main parts: (1) an architecture-independent core and (2) formal specifications of ARMv8 or, more precisely, a model automatically constructed on the basis of the formal specifications. With such a structure, the process of test program generator development consists mainly in creation of formal specifications, which saves efforts by reusing architecture-independent components. An architecture is described using the nML and MMUSL languages. The first one allows describing the microprocessor registers and syntax and semantics of the instructions. The second one is used to specify the memory subsystem organization (address spaces, various buffers and tables, address translation algorithms, etc.) The article describes characteristics of the developed generator and gives a comparison with the existing analogs.

Keywords

microprocessors, instruction set specification, functional verification, test program generation, ARM, nML, MicroTESK

Edition

Proceedings of the Institute for System Programming, vol. 28, issue 6, 2016, pp. 87-102.

ISSN 2220-6426 (Online), ISSN 2079-8156 (Print).

DOI: 10.15514/ISPRAS-2016-28(6)-6

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