Proceedings of ISP RAS


Verification of 10 Gigabit Ethernet Controllers

M.V. Petrochenkov (MCST, Moscow, Russia)
R.E. Mushtakov (MCST, Moscow, Russia)
I.A. Stotland (MCST, Moscow, Russia)

Abstract

This article proposes approaches used to verify 10 Gigabit Ethernet controllers developed by MCST. We present principles of the device operation – they provide a set of memory-mapped registers and use direct memory access, and their characteristics. We describe a set of approaches used to verify such devices – prototype based verification, system and stand-alone verification. We provide the motivation for the chosen approach – combination of system verification with stand-alone verification of its single component. The structure of the test systems that we used to verify devices and their components are presented. Test system of the controller transmits Ethernet frames to the network and receives frames from it. Algorithms to transfer packet to representation used by the device were implemented. Stand-alone test system was developed for a connector module between internal device buses and its external interface. Test systems were developed using UVM. This methodology and structure of test systems allowed to reuse components in a different systems. A set of test scenarios used to verify the device is described. The examination of network characteristics of the controller is very important in the verification process. Some approaches and techniques for throughput measuring and modes of device operations for the measurement are described. We present measured throughput in different modes. In conclusion, we provide a list of found errors and their distribution by different types of functionality they affected.

Keywords

10 Gigabit Ethernet; network interface controller; verification; throughput; UVM; test system

Edition

Proceedings of the Institute for System Programming, vol. 29, issue 4, 2017, pp. 257-268.

ISSN 2220-6426 (Online), ISSN 2079-8156 (Print).

DOI: 10.15514/ISPRAS-2017-29(4)-17

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