An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates.
In this paper we describe an approach to automated test programs generation intended for microprocessor verification. The approach is based on formal specification of microprocessor ISA and description of pipeline hazards templates. The use of formal specifications allows automating development of test program generators and systematizing control logic verification. Since the approach is underlain by high-level descriptions, all specifications and templates developed, as well as the constructed test programs, can be easily reused when the processor’s microarchitecture changes. It makes it possible to apply the methodology in early stages of a microprocessor development cycle when the design is frequently modified.Полный текст статьи в формате pdf (на английском)
Proceedings of the 4th Spring/Summer young Researchers Colloquium on Software Engineering, pp.130-135, 2010.