Simulation-Based Verification with Time-Abstract Models.
Simulation-based verification is a widely-spread approach to ensure functional correctness of hardware designs [1,2]. It is usually done by co-simulating a design under verification with an independently created reference model and checking conformance of their reactions. To reduce verification expenses, abstract models are commonly used (they are simpler, less error-prone and more reusable). Design timing (decomposition of operations into micro-operations and scheduling of those micro-operations) is the main object for abstraction. However, there are several problems in using time-abstract reference models for simulation-based verification. The paper discusses some of the problems and suggests simple, practice-oriented techniques to solve them.
Design & Test Symposium (EWDTS), 2011 9th East-West, 43-47.