Construction of test programs to check memory management subsystem of the microprocessors.
The thesis is devoted to the building of test programs for the core-level verification of microprocessors models. It helps to increase microprocessors quality and detect of defects at early stages of development. The core-level verification is performed for a microprocessor model at whole. Test programs are assembly programs targeted to specific situations in microprocessor behavior. Existing microprocessors require many test programs, so automatization of test program generation will be a perspective approach to the full verification of the microprocessors models. The thesis is based on existing ideas and approaches of test program generation. It proposes approaches for dealing with such behavior situations which will be impossible for generation later. The best application of the approaches proposed in the thesis is the generation of test programs for memory management units (MMU), i.e. for caching and virtual addresses translation. The thesis proposes new definitions for a lot of eviction strategies of caches. These definitions allow to decrease complexity of test programs generation and to use the proposed methods for practical eviction strategies.Full text of the paper in pdf (in Russian)
Diss. Institute for System Programming of the Russian Academy of Sciences, 2010.