Ivannikov Institute for System Programming of the RAS

A Method of EFSM Models Extraction from HDL Descriptions:Application to Functional Verification.


A.Kamkin, S. Smolov


The complexity of digital hardware systems steadily grows that bottlenecks their correctness checking, i.e. of functional verification. Automated methods of hardware verification are often based on models that are suitable for test generation and formal property checking. In this paper a new approach for extraction of extended finite state machine models from HDL descriptions is given, and the possibilities of such model usage in verification process are discussed.


hardware design, functional verification, static analysis, functional test generation, automata synthesis, extended finite state machines, guarded actions


The Proceedings of VI All-Russia Science & Technology Conference "Problems of Advanced Micro- and Nanoelectronic Systems Development", Vol. II. P. 113-118.

Research Group

Software Engineering

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